1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a circuit for driving a nonvolatile ferroelectric memory.
2. Background of the Related Art
A ferroelectric random access memory (FRAM) has a data processing speed as fast, as a DRAM and conserves data even after the power is turned off. The FRAM includes capacitors similar to the DRAM, but the capacitors have a ferroelectric substance for utilizing the characteristic of a high residual polarization of the ferroelectric substance in which data is not lost even after eliminating an electric field applied thereto.
FIG. 1 illustrates a general hysteresis loop of a ferroelectric substance. As shown in the hysteresis loop in FIG. 1, a polarization induced by an electric field does not vanish, but remains at a certain portion ("d" or "a" state) even after the electric field is cleared due to an existence of a spontaneous polarization. These "d" and "a" states may be matched to binary values of "1" and "0" for use as a memory cell. The state in which a positive voltage is applied to a ferroelectric memory cell is a "c" state in FIG. 1, the state in which no voltage is applied thereafter is a "d" state. Opposite to this, if a negative voltage is applied to the ferroelectric memory cell, the state moves from the "d" to an "f" state, and the state in which no voltage is applied thereafter is an "a" state. If a positive voltage is applied again, the states moves to the "c" state via the "b" state. Thus, a data can be stored in stable states of "a" and "d". On the hysteresis loop, "c" and "d" states correspond to a binary logic value of "1", and "a" and "f" states correspond to a binary logic value "0".
FIG. 2 illustrates a unit cell of a background art ferroelectric memory having two unit cells. The unit cells of a background art ferroelectric memory are provided with a plurality of bitlines Bit_n, Bit_n+1 . . . formed in a direction, a wordline W/L formed in a direction crossing the bitline, a plateline P/L formed in the same direction with the wordline spaced therefrom, and unit cells C111, C112, . . . each formed between the bitlines, the wordline and the plateline. Each unit cell C111, C121, . . . is provided with a transistor T1 having a gate connected to the wordline and a source connected to the bitline, and a ferroelectric capacitor FC1 having a first terminal connected to a drain of the transistor T1 and a second terminal connected to the plateline.
FIGS. 3a and 3b together illustrate a circuit for driving the background art one transistor/one capacitor (1T/1C) ferroelectric memory of FIG. 2. A reference voltage generator 1 generates a reference voltage, and a reference voltage stabilizer 2 having a plurality of transistors Q1.about.Q4 and a capacitor C1 stabilizes a reference voltage on two adjacent bitlines B1 and B2 because the reference voltage from the reference voltage generating part 1 can not be provided to a sense amplifier directly. A first reference voltage storage part 3 having a plurality of transistors Q6.about.Q7 and capacitors C2.about.C3 stores a logic value "1" and a logic value "0" in adjacent bit lines. A first equalizer 4 having a transistor Q5 equalizes adjacent two bitlines.
A first main cell array 5 connected to wordlines W/L and platelines P/L different from one another stores data, and a first sense amplifier 6 having a plurality of transistors Q10.about.Q15 and P-sense amplifiers PSA senses a data in a cell selected by the wordline from the plurality of cells in the main cell array part 5. A second main cell array 7 connected to wordlines and platelines different from one another stores data, and a second reference voltage storage 8 having a plurality of transistors Q28.about.Q29 and capacitors C9.about.C10 stores a logic value "1" and a logic value "0" in adjacent bit lines. A second sense amplifier 9 having a plurality of transistors Q16.about.Q25 and N-sense amplifiers NSA senses a data in the second main cell array 7.
FIG. 4 illustrates a timing diagram showing a write mode operation of the background art ferroelectric memory. First, when a chip enable signal CSBpad received externally is enabled from "high" to "low" and a write enable signal WEBpad also transits from "high" to "low", the write mode is started. An address decoding is started in the write mode, to transit a pulse applied to a selected wordline from "low" to "high" to a selected cell. In an interval where the wordline is thus held at "high", a corresponding plateline P/L is applied of a "high" signal for an interval and a "low" signal for an interval in a sequence and a corresponding bitline is applied of a "high" or "low" signal synchronous to the write enable signal, for writing a logic "1" or "0" on the selected cell. In other words, if a signal applied to the plateline is "low" in an interval where the bitline is applied of a "high" signal and the wordline is applied of a "high" signal, a logic value "1" is written in the ferroelectric capacitor. If a signal applied to the plateline is "high" and the bitline is applied of a "low" signal, a logic value "0" is written in the ferroelectric capacitor.
The operation for reading a data stored in a cell with the write mode operation will be explained with reference to FIG. 5. When the chip enable signal CSBpad is enabled from "high" to "low" externally, all bitlines are equalized to "low" by an equalizer signal before selection of a corresponding wordline. As shown in FIGS. 3a and 3b, when a "high" signal is applied to the equalizer 4 and a "high" signal is applied to transistors Q18 and Q19, grounding the bitlines through transistors Q18 and Q19, the bitlines are equalized to a low voltage Vss. The transistors Q5, Q18 and Q19 are turned off, disabling corresponding bitlines, and address is decoded for transiting a corresponding wordline from "low" to "high", to select a corresponding cell. Then, a "high" signal is applied to a plateline of the selected cell, to cancel data corresponding to a logic value "1" stored in a FRAM. If the FRAM is in storage of a logic value "0", a data corresponding to it will not be canceled. A cell with a canceled data and a cell with a data not canceled provide signals different from each other according to the aforementioned hysteresis loop principle. Data provided through the bitline is sensed by the sense amplifier of a logic value "1" or "0".
That is, referring to FIG. 1, since the case of a canceled data is a case when a state is changed from "d" to "f", and the case of a data not canceled is a case when a state is changed from "a" to "f", if the sense amplifier is enabled after a certain time, in the case of the canceled data, the data is amplified to provide a logic value "1", and, in the case of the data not canceled, the data is amplified to provide a logic value "0". After the sense amplifier amplifies and provides a signal, since the cell should be recovered of an original data, during "high" is applied to a corresponding line, the plateline is disabled from "high" to "low". However, in the background art 1T/1C ferroelectric memory, since the reference cell operates more often than the main memory cell in data input and output operations, the reference cell degrades rapidly.
Accordingly, the background art ferroelectric memory has various disadvantages. Since one reference cell of a ferroelectric substance of which ferroelectric property is not fully assured is provided for several hundreds of main memories cells for use in reading operation, requiring much more operation of the reference cell, the reference cell experiences a rapid degradation of the ferroelectric property, causing instability of the reference voltage and subsequent degradation of device operation performance and life time.